The present invention relates generally to synthesis of integrated circuits and more particularly to synthesis of memory in integrated circuits.
The development of the integrated circuit (IC) chip has been integral to the improvement and advancement of many industries. As the size of these ICs has reduced, their incorporation into a variety of applications has increased. While in some situations, a designer is able to use standard ICs for a desired function, in other situations, standard chips are unable to meet the precise needs of a designer. In such situations, designers often turn to an application specific integrated circuit (ASIC).
ASICs allow a designer to design an optimal circuit with desired customer specifications and functionality without conforming to the feature and performance limits of a standard chip. Typically, ASIC production begins with a set of circuit specifications. This design is then written in a hardware description language (HDL), such as VHDL, the IEEE standard, which is well known to those skilled in the art. The description is then "synthesized", i.e., a computer program uses the set of circuit specifications to design the circuitry of the IC, behavior of the circuit is verified, and a circuit layout is created. From the layout, a mask is formed and used for the IC chip production.
Techniques for the synthesis portion of ASIC creation are standardly aimed at producing gate-level netlists for gate arrays or standard cell implementations. While these methods for circuit design are well known, they traditionally fail to address the synthesis of memory components in ASIC designs.
For memory structures of an ASIC, conventionally either random logic synthesis or structural instantiation is used. However, with random logic synthesis, which generates a design of flip/flops, latches, and control logic to function as memory, designers are unable to take advantage of special architectures for memories that may give better results. On the other hand, structural instantiation requires that the designer manually create and complete the memory design including the memory control logic, so that they are unable to take full advantage of the synthesis tools. Therefore, neither of these techniques provides the designer with sufficient flexibility.
Approaches to providing separate memory synthesis have mainly focused on memory unit allocation based on analysis of variable or signal use in an HDL circuit description. Most of these approaches, however, have not examined characterizing memory elements and mapping generic memory units into technology-specific units. Existing tools that map generic components into technology-specific ones have focused on logic-level gates, such as NAND gates and NOR gates, simple sequential components, such as flip-flops and latches, or combinational datapath elements, such as ALUs, shifters, and adders. They have failed to address the mapping for complex memory structures, such as register files, RAMs, and ROMs. Therefore, what is needed is a method for synthesis of memory in ASICs that enhances ASIC design approaches by creating smaller circuits and providing designers with greater flexibility.